Anneals of semiconductor wafers for extended times at temperatures greater than or equal to 1000° C. are frequently required to form high resistance buried diffusions or to form low doping concentration deep n-type diffused wells especially for semiconductor wafers used for high voltage integrated circuit (IC) chips. Semiconductor wafers used to form integrated circuits include silicon, gallium arsenide, and other III-V materials used for integrated circuit manufacture. Most semiconductor wafers are silicon. Epitaxial semiconductor layers can be formed over silicon wafers and over other wafer types. During a high temperature anneal, volatile dopant atoms such as boron or phosphorus may out-diffuse from the walls of the anneal furnace or dopant atoms may out-diffuse from highly doped regions on the semiconductor wafer and counter-dope low doped regions elsewhere on the same semiconductor wafer, or on an adjacent wafer. The counter-doping may change the resistance of the low doped regions sufficiently to cause circuits on the semiconductor wafer to fail.
A cross section of a partially processed semiconductor wafer for manufacturing integrated circuits (ICs) 100 is shown in FIG. 1A. A lightly doped p-type epitaxial layer (P-EPI) 104 overlies a heavily doped p-type substrate (P+SUBSTRATE) 102. The p-type dopant is typically boron.
An n-type well (N WELL) 108 is formed in an upper portion of the P-EPI layer 104. The n-type dopant may be phosphorus or arsenic.
A p-type well (P WELL) 109 may also be formed in the upper portion of the P-EPI layer 104. P WELL 109 may be lightly doped with a dopant concentration slightly greater than the P-EPI layer 104 or may be medium doped with a dopant concentrations substantially higher than the P-EPI layer 104.
A first oxide layer 110 overlies the P-EPI layer 104 and N WELL 108. A second oxide layer 106 underlies the P+SUBSTRATE 102.
Silicon nitride layer 112 covers the oxide layer 106 on the backside of the semiconductor wafer. Silicon nitride is an effective barrier to volatile dopants such as boron and phosphorus. If the silicon nitride layer 112 is damaged by scratches or is defective and has defects prior to the high temperature anneal, out-diffusion of dopant atoms will occur from P+SUBSTRATE 102. Depositing silicon nitride layer 116 on the top side oxide layer 110 prior to a high temperature anneal prevents boron atoms that can diffuse out of the backside of the P+SUBSTRATE 102 from counter-doping N WELL 108 and from adding additional dopant to the P WELL 109 during the high temperature anneal. High temperature anneals {e.g., >=1000 degrees Celsius) are used for various processes such as formation of the diffused N WELL 108.
In other examples, semiconductor wafers with lightly doped regions may become counter-doped by the out-diffusion of volatile dopant atoms from highly doped regions on the same wafer or from a nearby wafer. Improvements are therefore needed.